Modeling software allows a developer to model the characteristics of a system, for example to evaluate if the system will meet the desired design requirements. Additionally, a modeled system may be rapidly reconfigured and various embodiments may be tested before a single piece of hardware is actually constructed. A model may be constructed using numerous pieces of currently available software, including MATLAB®, Simulink®, and Stateflow® from The MathWorks, Inc. of Natick, Mass. Upon creation of a model, and evaluation of the model, it is desirable to generate a system implementation in a format readily exported for use in the actual hardware fabrication. For example, the desired system implementation can be in a hardware description language such as VHDL, Verilog or SystemC.
The process of translating a system model into a system implementation is computationally intensive, and ordinarily performed in many steps. Conventionally, an intermediate representation is used to facilitate this process. Intermediate representations typically allow for a change in levels of abstraction from a source language to a target language and a corresponding system implementation.
Unfortunately, conventional solutions do not typically allow review or optimization of the intermediate representation prior to the generation of target language from the intermediate representation. Without an opportunity to review, modify or optimize the intermediate representation, the code generated by the intermediate representation may suffer from many deficiencies. These deficiencies may include increased execution time, increased ROM usage, increased RAM usage, and decreased readability of the code. A method enabling the optimization of an intermediate representation, increasing the efficiency and quality of the code generated by the intermediate representation, would be desirable.